Abstract
This chapter discusses memory diagnosis and built-in-self-repair. The purpose of memory diagnosis is twofold: (1) locating failures and subsequently repairing them, and (2) analyzing failures and defects and subsequently improving design and process. The chapter presents a hybrid built-in self-test (BIST) design-with diagnosis support-for embedded RAM. In association with the BIST design, the chapter also shows a diagnosis system (called MEGA) for automatic identification of the fault site and fault type. In addition to the fault locations necessary for repair, the syndromes of the detected faults can also be exported by the BIST circuit. By recording the fault locations and syndromes, the diagnosis system can identify the fault type of each faulty cell. Finally, this chapter presents a built-in self-repair (BISR) scheme for memories with 2D redundancy structures. The BISR design is composed of a BIST module and a built-in redundancy analysis (BIRA) module. It supports three test modes: (1) main memory testing, (2) spare memory testing, and (3) repair. The BIRA module also serves as the reconfiguration (address remapping) unit in normal mode.
| Original language | English |
|---|---|
| Title of host publication | VLSI Test Principles and Architectures |
| Publisher | Elsevier Inc. |
| Pages | 517-555 |
| Number of pages | 39 |
| ISBN (Print) | 9780123705976 |
| DOIs | |
| Publication status | Published - 2006 Dec 1 |
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All Science Journal Classification (ASJC) codes
- Business, Management and Accounting(all)
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Memory diagnosis and built-in self-repair. / Wu, Cheng Wen.
VLSI Test Principles and Architectures. Elsevier Inc., 2006. p. 517-555.Research output: Chapter in Book/Report/Conference proceeding › Chapter
TY - CHAP
T1 - Memory diagnosis and built-in self-repair
AU - Wu, Cheng Wen
PY - 2006/12/1
Y1 - 2006/12/1
N2 - This chapter discusses memory diagnosis and built-in-self-repair. The purpose of memory diagnosis is twofold: (1) locating failures and subsequently repairing them, and (2) analyzing failures and defects and subsequently improving design and process. The chapter presents a hybrid built-in self-test (BIST) design-with diagnosis support-for embedded RAM. In association with the BIST design, the chapter also shows a diagnosis system (called MEGA) for automatic identification of the fault site and fault type. In addition to the fault locations necessary for repair, the syndromes of the detected faults can also be exported by the BIST circuit. By recording the fault locations and syndromes, the diagnosis system can identify the fault type of each faulty cell. Finally, this chapter presents a built-in self-repair (BISR) scheme for memories with 2D redundancy structures. The BISR design is composed of a BIST module and a built-in redundancy analysis (BIRA) module. It supports three test modes: (1) main memory testing, (2) spare memory testing, and (3) repair. The BIRA module also serves as the reconfiguration (address remapping) unit in normal mode.
AB - This chapter discusses memory diagnosis and built-in-self-repair. The purpose of memory diagnosis is twofold: (1) locating failures and subsequently repairing them, and (2) analyzing failures and defects and subsequently improving design and process. The chapter presents a hybrid built-in self-test (BIST) design-with diagnosis support-for embedded RAM. In association with the BIST design, the chapter also shows a diagnosis system (called MEGA) for automatic identification of the fault site and fault type. In addition to the fault locations necessary for repair, the syndromes of the detected faults can also be exported by the BIST circuit. By recording the fault locations and syndromes, the diagnosis system can identify the fault type of each faulty cell. Finally, this chapter presents a built-in self-repair (BISR) scheme for memories with 2D redundancy structures. The BISR design is composed of a BIST module and a built-in redundancy analysis (BIRA) module. It supports three test modes: (1) main memory testing, (2) spare memory testing, and (3) repair. The BIRA module also serves as the reconfiguration (address remapping) unit in normal mode.
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UR - http://www.scopus.com/inward/citedby.url?scp=84882477101&partnerID=8YFLogxK
U2 - 10.1016/B978-012370597-6/50013-5
DO - 10.1016/B978-012370597-6/50013-5
M3 - Chapter
AN - SCOPUS:84882477101
SN - 9780123705976
SP - 517
EP - 555
BT - VLSI Test Principles and Architectures
PB - Elsevier Inc.
ER -