Memory testing and built-in self-test

Research output: Chapter in Book/Report/Conference proceedingChapter


This chapter discusses important aspects of semiconductor memory testing, including fault models, test algorithms, fault simulation, automatic test algorithm generation, and BIST. The BIST architecture presented in this chapter supports March-based tests and diagnosis. It presents a memory fault simulator called random access memory simulator for error screening (RAMSES), which consists of a simulation engine and numerous fault descriptors. The simulation engine reads the test inputs and sets the operation flags for each memory cell. Fault coverage is determined by checking the fault descriptors for predefined conditions. The test algorithm generator by simulation (TAGS) is then presented, which is based on RAMSES and March test algorithms. March tests have been widely considered to be the most efficient for conventional RAM fault models. This chapter also discusses memory built-in self-test (BIST). Finally, the chapter addresses a memory BIST compiler called BRAINS (Bist for Ram IN Seconds) which supports major types of SRAM and DRAM by using novel BIST templates and memory specification techniques.

Original languageEnglish
Title of host publicationVLSI Test Principles and Architectures
PublisherElsevier Inc.
Number of pages55
ISBN (Print)9780123705976
Publication statusPublished - 2006 Dec 1

All Science Journal Classification (ASJC) codes

  • Business, Management and Accounting(all)

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    Wu, C. W. (2006). Memory testing and built-in self-test. In VLSI Test Principles and Architectures (pp. 461-515). Elsevier Inc..