Method of fabricating Thin Transistor and Top-gate Type Thin Film Transustor

Chie Gau (Inventor)

Research output: Patent

Abstract

A method of fabricating a thin film transistor (TFT) and a top-gate type thin film transistor are disclosed, the method of fabricating a TFT of the present invention comprises steps: (A) providing a substrate; (B) forming a source electrode, a drain electrode, and SWCNT (singled-walled carbon nanotubes) layer on the substrate, in which the source electrode and the drain electrode are spaced in a distance and the SWCNT layer is located between the source electrode and the drain electrode; (C) forming a gate oxide layer on the SWCNT layer; (D) annealing the gate oxide layer with oxygen or nitrogen gas; and (E) forming a gate electrode on the gate oxide layer; wherein the temperature used in the step (D) for annealing is a 500° C. to 600° C.
Original languageEnglish
Patent number特許地5553856?
Publication statusPublished - 2012 Nov 29

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transistors
electrodes
thin films
carbon nanotubes
oxides
inventions
annealing
nitrogen
oxygen
gases
temperature

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Gau, Chie (Inventor). / Method of fabricating Thin Transistor and Top-gate Type Thin Film Transustor. Patent No.: 特許地5553856?.
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abstract = "A method of fabricating a thin film transistor (TFT) and a top-gate type thin film transistor are disclosed, the method of fabricating a TFT of the present invention comprises steps: (A) providing a substrate; (B) forming a source electrode, a drain electrode, and SWCNT (singled-walled carbon nanotubes) layer on the substrate, in which the source electrode and the drain electrode are spaced in a distance and the SWCNT layer is located between the source electrode and the drain electrode; (C) forming a gate oxide layer on the SWCNT layer; (D) annealing the gate oxide layer with oxygen or nitrogen gas; and (E) forming a gate electrode on the gate oxide layer; wherein the temperature used in the step (D) for annealing is a 500° C. to 600° C.",
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year = "2012",
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Method of fabricating Thin Transistor and Top-gate Type Thin Film Transustor. / Gau, Chie (Inventor).

Patent No.: 特許地5553856?.

Research output: Patent

TY - PAT

T1 - Method of fabricating Thin Transistor and Top-gate Type Thin Film Transustor

AU - Gau, Chie

PY - 2012/11/29

Y1 - 2012/11/29

N2 - A method of fabricating a thin film transistor (TFT) and a top-gate type thin film transistor are disclosed, the method of fabricating a TFT of the present invention comprises steps: (A) providing a substrate; (B) forming a source electrode, a drain electrode, and SWCNT (singled-walled carbon nanotubes) layer on the substrate, in which the source electrode and the drain electrode are spaced in a distance and the SWCNT layer is located between the source electrode and the drain electrode; (C) forming a gate oxide layer on the SWCNT layer; (D) annealing the gate oxide layer with oxygen or nitrogen gas; and (E) forming a gate electrode on the gate oxide layer; wherein the temperature used in the step (D) for annealing is a 500° C. to 600° C.

AB - A method of fabricating a thin film transistor (TFT) and a top-gate type thin film transistor are disclosed, the method of fabricating a TFT of the present invention comprises steps: (A) providing a substrate; (B) forming a source electrode, a drain electrode, and SWCNT (singled-walled carbon nanotubes) layer on the substrate, in which the source electrode and the drain electrode are spaced in a distance and the SWCNT layer is located between the source electrode and the drain electrode; (C) forming a gate oxide layer on the SWCNT layer; (D) annealing the gate oxide layer with oxygen or nitrogen gas; and (E) forming a gate electrode on the gate oxide layer; wherein the temperature used in the step (D) for annealing is a 500° C. to 600° C.

M3 - Patent

M1 - 特許地5553856?

ER -