Microelectronics roadmap: From ultimate CMOS to quantum information systems

The ITRS shows that the scaling effort will continue to a few tens of nanometers. In this talk, I will discuss the ITRS roadmap leading to the ultimate CMOS and then extrapolate to "Nanoelectronics". The major challenges are the fundamental limit of CMOS scaling and the increased number of global interconnects. Along the path to ultimate CMOS, vertical MOSFET and other related devices will be discussed. As we approach to the nanometer scale, quantum behaviors will play an important role. The question is how to continue the Moore's law in increasing the functional throughput per unit cost. This talk will describe some examples for potential off-the-roadmap types of "disruptive technologies" as a base for mutual discussion. Among them are using quantum-tunneling devices to increase the functional throughput per device count. In another direction, one may look at alternate architectures such as cellular automata, in which only nearest neighbor interconnects are needed and this type of architectures is most suitable for self-assembled fabrication of nanostructures. From the technology point of view, one potential new scheme to attain the low cost fabrication of nanostructures is self-assembly technique. Well-controlled placement of self-organized structures will be discussed. In this scheme, semiconductor quantum dots have been grown on Si. The size, shape and density of those dots can be controlled by growth temperature, deposited coverage and doping. Cooperative, well-organized Ge quantum dots have been achieved and they offered the potential applications of dot arrays for potential cellular systems. Eventually, entirely new massive parallel quantum computation systems may evolve. A possible semiconductor implementation based on SiGe nanostructures will be discussed.