Abstract
A fast multiple input signature register (MISR) computation algorithm for signature simulation is proposed. Based on the linear compaction algorithm the modularity property of a single input signature register (SISR), and the sparsity of the error-domain input, some new accelerating schemes - partial input look-up tables and reverse zero-checking policy - are developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the linear compaction algorithm. Though originally derived for SISR, this algorithm is applicable to MISR by a simple conversion procedure or a bit-adjusting scheme with little effort. Consequently, a very fast MISR signature simulation can be achieved.
| Original language | English |
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| Pages (from-to) | 213-218 |
| Number of pages | 6 |
| Journal | Proceedings of the Asian Test Symposium |
| Publication status | Published - 1996 Dec 1 |
| Event | Proceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan Duration: 1996 Nov 20 → 1996 Nov 22 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering