Model of asynchronous finite state machines and their pipelined structures

Ming-Der Shieh, Chin Long Wey, P. David Fisher

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The restrictions frequently imposed on asynchronous sequential logic circuits are that they assume the fundamental mode operation with single input change, i.e., input cannot change until the circuit stabilizes. As a result, the design of asynchronous finite state machines (AFSMs) has been limited because multiple-input changes are disallowed. This paper presents a new architecture for designing AFSMs with completion signals, where the completion signal is generated whenever both outputs and internal states stabilize. Results will show that the proposed design allows multiple-input changes and is free of races and hazards. Based on the proposed architecture, a pipelined AFSMs structure is also presented.

Original languageEnglish
Title of host publication1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages659-662
Number of pages4
ISBN (Electronic)0780305108
DOIs
Publication statusPublished - 1992 Jan 1
Event35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States
Duration: 1992 Aug 91992 Aug 12

Publication series

NameMidwest Symposium on Circuits and Systems
Volume1992-August
ISSN (Print)1548-3746

Conference

Conference35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
Country/TerritoryUnited States
CityWashington
Period92-08-0992-08-12

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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