Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

S. Venugopalan; Y. S. Chauhan; Darsen Lu; M. A. Karim; Ali M. Niknejad; Chenming Hu

doi:10.1109/NVMTS.2011.6137100

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

S. Venugopalan, Y. S. Chauhan, Darsen Lu, M. A. Karim, Ali M. Niknejad, Chenming Hu

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

Original language	English
Pages	125-128
Number of pages	4
DOIs	https://doi.org/10.1109/NVMTS.2011.6137100
Publication status	Published - 2011 Dec 1
Event	2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 - Shanghai, China Duration: 2011 Nov 7 → 2011 Nov 9

Other

Other	2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011
Country/Territory	China
City	Shanghai
Period	11-11-07 → 11-11-09

All Science Journal Classification (ASJC) codes

Hardware and Architecture

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10.1109/NVMTS.2011.6137100

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title = "Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations",

abstract = "In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.",

author = "S. Venugopalan and Chauhan, {Y. S.} and Darsen Lu and Karim, {M. A.} and Niknejad, {Ali M.} and Chenming Hu",

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doi = "10.1109/NVMTS.2011.6137100",

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Venugopalan, S, Chauhan, YS, Lu, D, Karim, MA, Niknejad, AM & Hu, C 2011, 'Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations', Paper presented at 2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011, Shanghai, China, 11-11-07 - 11-11-09 pp. 125-128. https://doi.org/10.1109/NVMTS.2011.6137100

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations. / Venugopalan, S.; Chauhan, Y. S.; Lu, Darsen; Karim, M. A.; Niknejad, Ali M.; Hu, Chenming.

2011. 125-128 Paper presented at 2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011, Shanghai, China.

Research output: Contribution to conference › Paper › peer-review

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AU - Venugopalan, S.

AU - Chauhan, Y. S.

AU - Lu, Darsen

AU - Karim, M. A.

AU - Niknejad, Ali M.

AU - Hu, Chenming

PY - 2011/12/1

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N2 - In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

AB - In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

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Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

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