Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

S. Venugopalan, Y. S. Chauhan, Darsen Lu, M. A. Karim, Ali M. Niknejad, Chenming Hu

Research output: Contribution to conferencePaperpeer-review

2 Citations (Scopus)

Abstract

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

Original languageEnglish
Pages125-128
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 - Shanghai, China
Duration: 2011 Nov 72011 Nov 9

Other

Other2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011
CountryChina
CityShanghai
Period11-11-0711-11-09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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