Abstract
In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.
Original language | English |
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Pages | 125-128 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2011 Dec 1 |
Event | 2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 - Shanghai, China Duration: 2011 Nov 7 → 2011 Nov 9 |
Other
Other | 2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 |
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Country/Territory | China |
City | Shanghai |
Period | 11-11-07 → 11-11-09 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture