Modeling of Bilayer Modulated RRAM and Its Array Performance for Compute-in-Memory Applications

Jia Wei Lee; Tzu Chin Chou; Po An Chen; Meng Hsueh Chiang

doi:10.1109/JXCDC.2023.3311899

Modeling of Bilayer Modulated RRAM and Its Array Performance for Compute-in-Memory Applications

Jia Wei Lee, Tzu Chin Chou, Po An Chen, Meng Hsueh Chiang

Doctoral Degree Program on Nano-Integrated-Circuit Engineering

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

This article presents a modified compact model of resistive random access memory (RRAM) with a tunneling barrier. The bilayer modulated RRAM can be integrated into a higher density array, reducing leakage current in standby mode. The model demonstrates current transition behavior from low- to high-bias regions by considering both bulk-limited and electrode-limited transport mechanisms. This model can evaluate RRAM array performance under various pulsing conditions and device parameter variations with calibrated model cards. The compute-in-memory application requires precise current sum results hindered by the wire resistance loading effect. This study also evaluates various sizes of arrays suitable for performance improvement.

Original language	English
Pages (from-to)	151-158
Number of pages	8
Journal	IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Volume	9
Issue number	2
DOIs	https://doi.org/10.1109/JXCDC.2023.3311899
Publication status	Published - 2023 Dec 1

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/JXCDC.2023.3311899

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abstract = "This article presents a modified compact model of resistive random access memory (RRAM) with a tunneling barrier. The bilayer modulated RRAM can be integrated into a higher density array, reducing leakage current in standby mode. The model demonstrates current transition behavior from low- to high-bias regions by considering both bulk-limited and electrode-limited transport mechanisms. This model can evaluate RRAM array performance under various pulsing conditions and device parameter variations with calibrated model cards. The compute-in-memory application requires precise current sum results hindered by the wire resistance loading effect. This study also evaluates various sizes of arrays suitable for performance improvement.",

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AB - This article presents a modified compact model of resistive random access memory (RRAM) with a tunneling barrier. The bilayer modulated RRAM can be integrated into a higher density array, reducing leakage current in standby mode. The model demonstrates current transition behavior from low- to high-bias regions by considering both bulk-limited and electrode-limited transport mechanisms. This model can evaluate RRAM array performance under various pulsing conditions and device parameter variations with calibrated model cards. The compute-in-memory application requires precise current sum results hindered by the wire resistance loading effect. This study also evaluates various sizes of arrays suitable for performance improvement.

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Modeling of Bilayer Modulated RRAM and Its Array Performance for Compute-in-Memory Applications

Abstract

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