Modeling of RRAM with Embedded Tunneling Barrier and Its Application in Logic in Memory

Jia Wei Lee, Meng Hsueh Chiang

Research output: Contribution to journalArticlepeer-review

Abstract

This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.

Original languageEnglish
Article number9137335
Pages (from-to)1390-1396
Number of pages7
JournalIEEE Journal of the Electron Devices Society
Volume8
DOIs
Publication statusPublished - 2020

All Science Journal Classification (ASJC) codes

  • Biotechnology
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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