Abstract
This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.
Original language | English |
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Article number | 9137335 |
Pages (from-to) | 1390-1396 |
Number of pages | 7 |
Journal | IEEE Journal of the Electron Devices Society |
Volume | 8 |
DOIs | |
Publication status | Published - 2020 |
All Science Journal Classification (ASJC) codes
- Biotechnology
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering