Modeling of RRAM with Embedded Tunneling Barrier and Its Application in Logic in Memory

Jia Wei Lee; Meng Hsueh Chiang

doi:10.1109/JEDS.2020.3008172

Modeling of RRAM with Embedded Tunneling Barrier and Its Application in Logic in Memory

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Abstract

This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.

Original language	English
Article number	9137335
Pages (from-to)	1390-1396
Number of pages	7
Journal	IEEE Journal of the Electron Devices Society
Volume	8
DOIs	https://doi.org/10.1109/JEDS.2020.3008172
Publication status	Published - 2020

All Science Journal Classification (ASJC) codes

Biotechnology
Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/JEDS.2020.3008172

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title = "Modeling of RRAM with Embedded Tunneling Barrier and Its Application in Logic in Memory",

abstract = "This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.",

author = "Lee, {Jia Wei} and Chiang, {Meng Hsueh}",

note = "Funding Information: This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST 108-2221-E-006-019, and in part by the National Center for High-Performance Computing and Taiwan Semiconductor Research Institute. Publisher Copyright: {\textcopyright} 2013 IEEE.",

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Modeling of RRAM with Embedded Tunneling Barrier and Its Application in Logic in Memory

Abstract

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