Modular design of high-efficiency hardware median filter architecture

Shih Hsiang Lin, Pei Yin Chen, Chih Kun Hsu

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

This paper presents the hardware design and implementation of 1-D median filter that uses modular architecture, which produces median results hierarchically. Different types of submodules could be applied to form a customized architecture in order to meet different constraints and requirements. Complete analysis and hardware-oriented optimization were performed to achieve the optimal configurations when the input size and data length were changed. As the data length increases, the required resources and latency increase linearly, while the maximal operation frequency is nearly independent to data length. When our filter is synthesized using 90-nm process technology, its operating frequency could achieve more than 2000 MHz and resource consumption is reduced by 23.29% when compared with the state-of-the-art design. The experimental results show that the proposed cascaded architecture is superior to existing designs in terms of maximal operating speed and resource costs.

Original languageEnglish
Pages (from-to)1929-1940
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume65
Issue number6
DOIs
Publication statusPublished - 2018 Jun

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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