MRAM defect analysis and fault modeling

Chin Lung Su, Rei Fu Huang, Cheng Wen Wu, Chien Chung Hung, Ming Jer Kao, Yeong Jar Chang, Wen Ching Wu

Research output: Contribution to journalConference article

18 Citations (Scopus)

Abstract

With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM has a high speed and does not need high supply voltage for Read/Write operations, so it has the advantages of RAM and flash memory, making it a potentially good choice for SOC. The testing of MRAM, however, has not been fully investigated. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. We have built a SPICE model of MRAM cell and performed defect injection and simulation of a real MRAM circuit. The circuit has been implemented and fabricated with a novel 0.18μm technology. The simulation results regarding the correlation between the defects and conventional fault models show that most of the defects can be covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault.

Original languageEnglish
Pages (from-to)124-133
Number of pages10
JournalProceedings - International Test Conference
Publication statusPublished - 2004 Dec 1
EventProceedings - International Test Conference 2004 - Charlotte, NC, United States
Duration: 2004 Oct 262004 Oct 28

Fingerprint

Random Access
Fault
Defects
Data storage equipment
Modeling
Flash Memory
Chip
Flash memory
Random access storage
Networks (circuits)
SPICE
Kink
Model
Injection
Simulation
High Speed
Classify
Voltage
Cover
Testing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Su, C. L., Huang, R. F., Wu, C. W., Hung, C. C., Kao, M. J., Chang, Y. J., & Wu, W. C. (2004). MRAM defect analysis and fault modeling. Proceedings - International Test Conference, 124-133.
Su, Chin Lung ; Huang, Rei Fu ; Wu, Cheng Wen ; Hung, Chien Chung ; Kao, Ming Jer ; Chang, Yeong Jar ; Wu, Wen Ching. / MRAM defect analysis and fault modeling. In: Proceedings - International Test Conference. 2004 ; pp. 124-133.
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Su, CL, Huang, RF, Wu, CW, Hung, CC, Kao, MJ, Chang, YJ & Wu, WC 2004, 'MRAM defect analysis and fault modeling', Proceedings - International Test Conference, pp. 124-133.

MRAM defect analysis and fault modeling. / Su, Chin Lung; Huang, Rei Fu; Wu, Cheng Wen; Hung, Chien Chung; Kao, Ming Jer; Chang, Yeong Jar; Wu, Wen Ching.

In: Proceedings - International Test Conference, 01.12.2004, p. 124-133.

Research output: Contribution to journalConference article

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AU - Su, Chin Lung

AU - Huang, Rei Fu

AU - Wu, Cheng Wen

AU - Hung, Chien Chung

AU - Kao, Ming Jer

AU - Chang, Yeong Jar

AU - Wu, Wen Ching

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N2 - With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM has a high speed and does not need high supply voltage for Read/Write operations, so it has the advantages of RAM and flash memory, making it a potentially good choice for SOC. The testing of MRAM, however, has not been fully investigated. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. We have built a SPICE model of MRAM cell and performed defect injection and simulation of a real MRAM circuit. The circuit has been implemented and fabricated with a novel 0.18μm technology. The simulation results regarding the correlation between the defects and conventional fault models show that most of the defects can be covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault.

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Su CL, Huang RF, Wu CW, Hung CC, Kao MJ, Chang YJ et al. MRAM defect analysis and fault modeling. Proceedings - International Test Conference. 2004 Dec 1;124-133.