M2-B-Quadro: A scalable optical switch architecture for contention resolution

Wang Rong Chang; Hui Tang Lin; Ho Ting Wu

doi:10.1109/APCC.2005.1554174

M²-B-Quadro: A scalable optical switch architecture for contention resolution

Wang Rong Chang, Hui Tang Lin, Ho Ting Wu

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a new switching architecture to be used in all optical networks. The proposed switch, denoted as M²-B-Quadro, is an extension of the 2 × 2 two-stage Multi-buffer Bypass Quadro (M-B-Quadro) switch introduced by the current authors in [1]. By incorporating bypass lines and employing a novel switch control strategy, denoted as POS, the proposed switching node effectively resolves packet contentions and provides a substantial reduction in the packet deflection probability. We also demonstrate that such architecture can also be applied to design a generic multiple stages switch of a larger number of input/output ports with superior performances.

Original language	English
Title of host publication	2005 Asia-Pacific Conference on Communications
Pages	807-811
Number of pages	5
DOIs	https://doi.org/10.1109/APCC.2005.1554174
Publication status	Published - 2005 Dec 1
Event	2005 Asia-Pacific Conference on Communications - Perth, Western Australia, Australia Duration: 2005 Oct 3 → 2005 Oct 5

Publication series

Name	2005 Asia-Pacific Conference on Communications
Volume	2005

Other

Other	2005 Asia-Pacific Conference on Communications
Country/Territory	Australia
City	Perth, Western Australia
Period	05-10-03 → 05-10-05

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/APCC.2005.1554174

Cite this

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title = "M2-B-Quadro: A scalable optical switch architecture for contention resolution",

abstract = "This paper proposes a new switching architecture to be used in all optical networks. The proposed switch, denoted as M2-B-Quadro, is an extension of the 2 × 2 two-stage Multi-buffer Bypass Quadro (M-B-Quadro) switch introduced by the current authors in [1]. By incorporating bypass lines and employing a novel switch control strategy, denoted as POS, the proposed switching node effectively resolves packet contentions and provides a substantial reduction in the packet deflection probability. We also demonstrate that such architecture can also be applied to design a generic multiple stages switch of a larger number of input/output ports with superior performances.",

author = "Chang, {Wang Rong} and Lin, {Hui Tang} and Wu, {Ho Ting}",

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note = "2005 Asia-Pacific Conference on Communications ; Conference date: 03-10-2005 Through 05-10-2005",

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Chang, WR, Lin, HT & Wu, HT 2005, M²-B-Quadro: A scalable optical switch architecture for contention resolution. in 2005 Asia-Pacific Conference on Communications., 1554174, 2005 Asia-Pacific Conference on Communications, vol. 2005, pp. 807-811, 2005 Asia-Pacific Conference on Communications, Perth, Western Australia, Australia, 05-10-03. https://doi.org/10.1109/APCC.2005.1554174

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N2 - This paper proposes a new switching architecture to be used in all optical networks. The proposed switch, denoted as M2-B-Quadro, is an extension of the 2 × 2 two-stage Multi-buffer Bypass Quadro (M-B-Quadro) switch introduced by the current authors in [1]. By incorporating bypass lines and employing a novel switch control strategy, denoted as POS, the proposed switching node effectively resolves packet contentions and provides a substantial reduction in the packet deflection probability. We also demonstrate that such architecture can also be applied to design a generic multiple stages switch of a larger number of input/output ports with superior performances.

AB - This paper proposes a new switching architecture to be used in all optical networks. The proposed switch, denoted as M2-B-Quadro, is an extension of the 2 × 2 two-stage Multi-buffer Bypass Quadro (M-B-Quadro) switch introduced by the current authors in [1]. By incorporating bypass lines and employing a novel switch control strategy, denoted as POS, the proposed switching node effectively resolves packet contentions and provides a substantial reduction in the packet deflection probability. We also demonstrate that such architecture can also be applied to design a generic multiple stages switch of a larger number of input/output ports with superior performances.

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