TY - GEN
T1 - Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems
AU - Gupta, Subhanshu
AU - Tang, Yi
AU - Cheng, Kuang Wei
AU - Paramesh, Jeyanandh
AU - Allstot, David J.
PY - 2011
Y1 - 2011
N2 - Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two well-known limitations: slow convergence and increased computational complexity/power dissipation for higher adaptive filter orders and sampling frequencies. Half-(fs/2) and quarter-rate (f s/4) LMS calibration for oversampled A/D decimators are used to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (ΣΔ) ADC. Energy savings up to 30% compared to conventional full-rate (fs) schemes are confirmed using an Altera Stratix II field-programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2-2 cascade ΣΔ ADC implemented in 0.13μm CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the ΣΔ ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.
AB - Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two well-known limitations: slow convergence and increased computational complexity/power dissipation for higher adaptive filter orders and sampling frequencies. Half-(fs/2) and quarter-rate (f s/4) LMS calibration for oversampled A/D decimators are used to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (ΣΔ) ADC. Energy savings up to 30% compared to conventional full-rate (fs) schemes are confirmed using an Altera Stratix II field-programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2-2 cascade ΣΔ ADC implemented in 0.13μm CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the ΣΔ ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.
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U2 - 10.1109/ICASSP.2011.5946799
DO - 10.1109/ICASSP.2011.5946799
M3 - Conference contribution
AN - SCOPUS:80051621939
SN - 9781457705397
T3 - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
SP - 1585
EP - 1588
BT - 2011 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2011 - Proceedings
T2 - 36th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2011
Y2 - 22 May 2011 through 27 May 2011
ER -