Multiple-valued memory design by standard BiCMOS technique

Dong Shong Liang; Kwang Jow Gan; Jenq Jong Lu; Cheng Chi Tai; Cher Shiung Tsai; Geng Huang Lan; Yaw Hwang Chen

doi:10.1109/CSIE.2009.972

Multiple-valued memory design by standard BiCMOS technique

Dong Shong Liang, Kwang Jow Gan, Jenq Jong Lu, Cheng Chi Tai, Cher Shiung Tsai, Geng Huang Lan, Yaw Hwang Chen

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction- bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.

Original language	English
Title of host publication	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Publisher	IEEE Computer Society
Pages	596-599
Number of pages	4
ISBN (Print)	9780769535074
DOIs	https://doi.org/10.1109/CSIE.2009.972
Publication status	Published - 2009
Event	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009 - Los Angeles, CA, United States Duration: 2009 Mar 31 → 2009 Apr 2

Publication series

Name	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Volume	3

Other

Other	2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Country/Territory	United States
City	Los Angeles, CA
Period	09-03-31 → 09-04-02

All Science Journal Classification (ASJC) codes

Computer Science Applications
Hardware and Architecture
Information Systems
Software

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10.1109/CSIE.2009.972

Cite this

Liang, D. S., Gan, K. J., Lu, J. J., Tai, C. C., Tsai, C. S., Lan, G. H., & Chen, Y. H. (2009). Multiple-valued memory design by standard BiCMOS technique. In 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009 (pp. 596-599). Article 5170910 (2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009; Vol. 3). IEEE Computer Society. https://doi.org/10.1109/CSIE.2009.972

@inproceedings{c2dcc81e3ecb4d228e342cf37197d78a,

title = "Multiple-valued memory design by standard BiCMOS technique",

abstract = "A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction- bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.",

author = "Liang, {Dong Shong} and Gan, {Kwang Jow} and Lu, {Jenq Jong} and Tai, {Cheng Chi} and Tsai, {Cher Shiung} and Lan, {Geng Huang} and Chen, {Yaw Hwang}",

year = "2009",

doi = "10.1109/CSIE.2009.972",

language = "English",

isbn = "9780769535074",

series = "2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009",

publisher = "IEEE Computer Society",

pages = "596--599",

booktitle = "2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009",

address = "United States",

note = "2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009 ; Conference date: 31-03-2009 Through 02-04-2009",

}

Liang, DS, Gan, KJ, Lu, JJ, Tai, CC, Tsai, CS, Lan, GH & Chen, YH 2009, Multiple-valued memory design by standard BiCMOS technique. in 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009., 5170910, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, vol. 3, IEEE Computer Society, pp. 596-599, 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009, Los Angeles, CA, United States, 09-03-31. https://doi.org/10.1109/CSIE.2009.972

Multiple-valued memory design by standard BiCMOS technique. / Liang, Dong Shong; Gan, Kwang Jow; Lu, Jenq Jong et al.
2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009. IEEE Computer Society, 2009. p. 596-599 5170910 (2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Multiple-valued memory design by standard BiCMOS technique

AU - Liang, Dong Shong

AU - Gan, Kwang Jow

AU - Lu, Jenq Jong

AU - Tai, Cheng Chi

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AU - Lan, Geng Huang

AU - Chen, Yaw Hwang

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N2 - A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction- bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.

AB - A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction- bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.

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Y2 - 31 March 2009 through 2 April 2009

ER -

Multiple-valued memory design by standard BiCMOS technique

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