TY - JOUR
T1 - N-Shaped Negative Differential Resistance in a Transistor Structure With a Resistive Gate
AU - Wei, Houng Chi
AU - Wang, Yeong Her
AU - Houng, Mau Phon
N1 - Funding Information:
Manuscript received July 20, 1993; revised January 17, 1994. The review of this paper was arranged by Associate Editor N. Moll. This work was supported in pan by National Science Council of the Republic of China under Contract Number NSC-8 1-0404E006-612 and NSC-82-0404-E006-435. The authors are with the Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan, ROC. IEEE Log Number 9402588.
PY - 1994/8
Y1 - 1994/8
N2 - Voltage-controlled negative differential resistance (NDR) characteristics in a N-AlGaAs/p+-GaAs/n-GaAs transistor structure are proposed and demonstrated. The gate, made using self-aligned p-type diffusion, is placed in the n-GaAs collector layer instead of the p+-GaAs base layer, resulting in a so-called resistive gate. For a fixed gate voltage, the device current is modulated by the applied anode voltage. Under appropriate gate voltage with respect to the anode, the device shows good voltage-controllable NDR characteristics, including large peak-to-valley current ratios (PTV’s) and a voltage extension in the N-shaped curve which is equivalent to the common-emitter breakdown voltage in a transistor. A numerical model based on the transistor model for the carrier transport in this device, taking account of the influence of the applied anode voltage on the gate, is proposed. The experimental results show large room temperature PTV’s (e.g., 140 at a gate bias of 1.5 V) and large voltage extension in N-shaped curves (about 9 V). Reasonable agreement between theoretical and experimental results is observed.
AB - Voltage-controlled negative differential resistance (NDR) characteristics in a N-AlGaAs/p+-GaAs/n-GaAs transistor structure are proposed and demonstrated. The gate, made using self-aligned p-type diffusion, is placed in the n-GaAs collector layer instead of the p+-GaAs base layer, resulting in a so-called resistive gate. For a fixed gate voltage, the device current is modulated by the applied anode voltage. Under appropriate gate voltage with respect to the anode, the device shows good voltage-controllable NDR characteristics, including large peak-to-valley current ratios (PTV’s) and a voltage extension in the N-shaped curve which is equivalent to the common-emitter breakdown voltage in a transistor. A numerical model based on the transistor model for the carrier transport in this device, taking account of the influence of the applied anode voltage on the gate, is proposed. The experimental results show large room temperature PTV’s (e.g., 140 at a gate bias of 1.5 V) and large voltage extension in N-shaped curves (about 9 V). Reasonable agreement between theoretical and experimental results is observed.
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U2 - 10.1109/16.297725
DO - 10.1109/16.297725
M3 - Article
AN - SCOPUS:0028486086
VL - 41
SP - 1327
EP - 1333
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 8
ER -