Nano on nano

T. S. Yeoh; C. P. Liu; R. B. Swint; A. Gaur; V. C. Elarde; J. J. Coleman

doi:10.1109/MCD.2003.1203175

Nano on nano

T. S. Yeoh, C. P. Liu, R. B. Swint, A. Gaur, V. C. Elarde, J. J. Coleman

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

High-quality QD growth takes place in a narrow window of parameters. This window can be used to selectively grow QDs by altering the local chemistry of the surface by indium segregation. The final morphology of the segregated indium can be changed to organize the selectively grown QDs. Selective area epitaxy by indium segregation is not sensitive to lithographic process variations affecting growth rate and uniformity. Furthermore, it minimizes the number of processing and thermal steps that are detrimental to QDs. Its compatibility with traditional selective area and nanolithography techniques makes it a versatile tool for creating future devices.

Original language	English
Pages (from-to)	26-31
Number of pages	6
Journal	IEEE Circuits and Devices Magazine
Volume	19
Issue number	3
DOIs	https://doi.org/10.1109/MCD.2003.1203175
Publication status	Published - 2003 May

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Instrumentation
Electrical and Electronic Engineering

Access to Document

10.1109/MCD.2003.1203175

Cite this

@article{9df35466243d4dc7b5554132be6befba,

title = "Nano on nano",

abstract = "High-quality QD growth takes place in a narrow window of parameters. This window can be used to selectively grow QDs by altering the local chemistry of the surface by indium segregation. The final morphology of the segregated indium can be changed to organize the selectively grown QDs. Selective area epitaxy by indium segregation is not sensitive to lithographic process variations affecting growth rate and uniformity. Furthermore, it minimizes the number of processing and thermal steps that are detrimental to QDs. Its compatibility with traditional selective area and nanolithography techniques makes it a versatile tool for creating future devices.",

author = "Yeoh, {T. S.} and Liu, {C. P.} and Swint, {R. B.} and A. Gaur and Elarde, {V. C.} and Coleman, {J. J.}",

note = "Funding Information: This work was supported by NSF ECS 99-00258, the DARPA University Optoelectronics Centers program, and the U.S. Department of Energy under Award No. DEFG02-91ER45439.",

year = "2003",

month = may,

doi = "10.1109/MCD.2003.1203175",

language = "English",

volume = "19",

pages = "26--31",

journal = "IEEE Circuits and Devices Magazine",

issn = "8755-3996",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Nano on nano

AU - Yeoh, T. S.

AU - Liu, C. P.

AU - Swint, R. B.

AU - Gaur, A.

AU - Elarde, V. C.

AU - Coleman, J. J.

N1 - Funding Information: This work was supported by NSF ECS 99-00258, the DARPA University Optoelectronics Centers program, and the U.S. Department of Energy under Award No. DEFG02-91ER45439.

PY - 2003/5

Y1 - 2003/5

N2 - High-quality QD growth takes place in a narrow window of parameters. This window can be used to selectively grow QDs by altering the local chemistry of the surface by indium segregation. The final morphology of the segregated indium can be changed to organize the selectively grown QDs. Selective area epitaxy by indium segregation is not sensitive to lithographic process variations affecting growth rate and uniformity. Furthermore, it minimizes the number of processing and thermal steps that are detrimental to QDs. Its compatibility with traditional selective area and nanolithography techniques makes it a versatile tool for creating future devices.

AB - High-quality QD growth takes place in a narrow window of parameters. This window can be used to selectively grow QDs by altering the local chemistry of the surface by indium segregation. The final morphology of the segregated indium can be changed to organize the selectively grown QDs. Selective area epitaxy by indium segregation is not sensitive to lithographic process variations affecting growth rate and uniformity. Furthermore, it minimizes the number of processing and thermal steps that are detrimental to QDs. Its compatibility with traditional selective area and nanolithography techniques makes it a versatile tool for creating future devices.

UR - http://www.scopus.com/inward/record.url?scp=0038614674&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038614674&partnerID=8YFLogxK

U2 - 10.1109/MCD.2003.1203175

DO - 10.1109/MCD.2003.1203175

M3 - Article

AN - SCOPUS:0038614674

SN - 8755-3996

VL - 19

SP - 26

EP - 31

JO - IEEE Circuits and Devices Magazine

JF - IEEE Circuits and Devices Magazine

IS - 3

ER -

Nano on nano

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this