TY - JOUR
T1 - Nano scale computational architectures with Spin Wave Bus
AU - Khitun, Alexander
AU - Wang, Kang L.
N1 - Funding Information:
The authors want to thank Dr. K. Likharev and Dr. R. Kielh for valuable discussion. The work was supported in part by the MARCO-FENA center (Dr. Simon Thomas) and by DARPA (Dr. Dan Radack).
PY - 2005/9
Y1 - 2005/9
N2 - We propose and analyze a new kind of nano scale computational architectures using spin waves as a physical mechanism for device interconnection. Information is encoded into the phase of spin waves propagating in a ferromagnetic film - a Spin Wave Bus. We describe several possible logic devices utilizing spin waves. The performance of the proposed devices is illustrated by numerical modeling based on the experimental data for spin wave excitation and propagation in NiFe film. The key advantage of the proposed architectures is that information transmission is accomplished without charge transfer. Potentially, the architectures with Spin Wave Bus may be beneficial in terms of power consumption and resolve the interconnect problem. Another expected benefit is in the enhanced logic functionality. Using phase logic, it is possible to realize a number of logic functions in one device. These advantages make the architectures with a Spin Wave Bus very promising for application in ultra-high-density integrated circuits (more than 1010 devices per square inch).
AB - We propose and analyze a new kind of nano scale computational architectures using spin waves as a physical mechanism for device interconnection. Information is encoded into the phase of spin waves propagating in a ferromagnetic film - a Spin Wave Bus. We describe several possible logic devices utilizing spin waves. The performance of the proposed devices is illustrated by numerical modeling based on the experimental data for spin wave excitation and propagation in NiFe film. The key advantage of the proposed architectures is that information transmission is accomplished without charge transfer. Potentially, the architectures with Spin Wave Bus may be beneficial in terms of power consumption and resolve the interconnect problem. Another expected benefit is in the enhanced logic functionality. Using phase logic, it is possible to realize a number of logic functions in one device. These advantages make the architectures with a Spin Wave Bus very promising for application in ultra-high-density integrated circuits (more than 1010 devices per square inch).
UR - http://www.scopus.com/inward/record.url?scp=24044436569&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=24044436569&partnerID=8YFLogxK
U2 - 10.1016/j.spmi.2005.07.001
DO - 10.1016/j.spmi.2005.07.001
M3 - Article
AN - SCOPUS:24044436569
SN - 0749-6036
VL - 38
SP - 184
EP - 200
JO - Superlattices and Microstructures
JF - Superlattices and Microstructures
IS - 3
ER -