Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

C. J. Su, Y. T. Tang, Y. C. Tsou, P. J. Sung, F. J. Hou, C. J. Wang, S. T. Chung, C. Y. Hsieh, Y. S. Yeh, F. K. Hsueh, Kuo-Hsing Kao, S. S. Chuang, C. T. Wu, T. Y. You, Y. L. Jian, T. H. Chou, Y. L. Shen, B. Y. Chen, G. L. Luo, T. C. HongK. P. Huang, M. C. Chen, Y. J. Lee, T. S. Chao, T. Y. Tseng, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Yeong-Her Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO x (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al 2 O 3 IL results in paraelectric behavior, HZO on GeO x IL exhibits significant FE. High I on /I off (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L g ) of 60 nm and a FE-HZO/GeO x gate stack.

Original languageEnglish
Title of host publication2017 Symposium on VLSI Technology, VLSI Technology 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT152-T153
ISBN (Electronic)9784863486058
DOIs
Publication statusPublished - 2017 Jul 31
Event37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan
Duration: 2017 Jun 52017 Jun 8

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other37th Symposium on VLSI Technology, VLSI Technology 2017
CountryJapan
CityKyoto
Period17-06-0517-06-08

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Su, C. J., Tang, Y. T., Tsou, Y. C., Sung, P. J., Hou, F. J., Wang, C. J., Chung, S. T., Hsieh, C. Y., Yeh, Y. S., Hsueh, F. K., Kao, K-H., Chuang, S. S., Wu, C. T., You, T. Y., Jian, Y. L., Chou, T. H., Shen, Y. L., Chen, B. Y., Luo, G. L., ... Wang, Y-H. (2017). Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON In 2017 Symposium on VLSI Technology, VLSI Technology 2017 (pp. T152-T153). [7998159] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2017.7998159