We propose an integer linear programming-based formulation to improve the effectiveness of the transmission gate-based technique intended to reduce negative-bias temperature instability and leakage power consumption. We also propose a virtual input pin technique to improve leakage reduction and use path sensitization to reduce area overhead. Simulation results show that combining these techniques can achieve >51.18% delay improvement and 63.34% leakage power improvement with only 2.31% area overhead.
|Number of pages||5|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2014 Sep|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering