NEW 2-OR-3 LAYER CHANNEL ROUTER FOR VLSI LAYOUT.

Jer Min Jou, Jau Yien Lee, Bin Da Liu, Jhing Fa Wang, Gern Wang

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

A two- or three-layer greedy channel router, which is based on the extension of the dynamic adaptive generalized router (DAPRT) and can route a channel in two or three layers, is presented. The time complexity of the router is O(n multiplied by W), where n is the number of columns in a channel, and W is the width of a channel. The algorithm has been coded in Pascal and implemented on a VAX-11/780 computer. Results from several benchmark problems are evaluated. The router consistently outperforms several known routers in quality of wiring in three-layer routing. For example, it finds a ten-track solution for the three-layer Deutsch's difficult example, whereas all other known routers required 11 or more tracks; for the two-layer case, it also routes the problem with only 19 tracks.

Original languageEnglish
Pages (from-to)47-50
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 1987 Jan 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'NEW 2-OR-3 LAYER CHANNEL ROUTER FOR VLSI LAYOUT.'. Together they form a unique fingerprint.

Cite this