New architecture for analog boundary scan

Kuen-Jong Lee, Sheng Yih Jeng, Tian Pao Lee

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)


The IEEE Boundary Scan Standard 1149.1 has been widely used for digital circuit testing. A similar standard for analog circuits is yet to be set up. In this paper we propose a new analog boundary scan architecture which is similar to the IEEE Std. 1149.1. The basic analog boundary scan cell, the defined instructions, the associated operations, and the control circuitry are described. The advantages of this architecture include: (1) Signal at various test points can be sampled simultaneously, (2) test stimuli can be injected to various test points simultaneously, and (3) test stimuli loading and test response outputting can be done simultaneously.

Original languageEnglish
Pages (from-to)409-412
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 1995 Jan 1
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 1995 Apr 301995 May 3

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'New architecture for analog boundary scan'. Together they form a unique fingerprint.

Cite this