New fault simulator for large synchronous sequential circuits

A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. 1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. 2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. 3) All the multiple event faults are dynamically ordered for each test pattern such that the faults with the same faulty effects can be put into the same packet, so as to reduce the number of events created during simulation. 4) All the packets are propagated simultaneously; therefore, each gate is simulated only once for each test pattern, and while propagating packets, equivalent stem faults are also inserted into the packets and propagated as well. A memory sharing technique is used to reduce the memory overhead. Experimental results show that our fault simulator runs faster than PROOFS, HOPE, and improved HOPE (HOPE1.1) for large synchronous sequential benchmark circuits.