New fault simulator for large synchronous sequential circuits

Jer-Min Jou, Shung Chih Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. 1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. 2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. 3) All the multiple event faults are dynamically ordered for each test pattern such that the faults with the same faulty effects can be put into the same packet, so as to reduce the number of events created during simulation. 4) All the packets are propagated simultaneously; therefore, each gate is simulated only once for each test pattern, and while propagating packets, equivalent stem faults are also inserted into the packets and propagated as well. A memory sharing technique is used to reduce the memory overhead. Experimental results show that our fault simulator runs faster than PROOFS, HOPE, and improved HOPE (HOPE1.1) for large synchronous sequential benchmark circuits.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
PublisherIEEE
Pages466-471
Number of pages6
Publication statusPublished - 1994
EventProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan
Duration: 1994 Dec 51994 Dec 8

Other

OtherProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
CityTaipei, Taiwan
Period94-12-0594-12-08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Jou, J-M., & Chen, S. C. (1994). New fault simulator for large synchronous sequential circuits. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings (pp. 466-471). IEEE.