Abstract
In the paper, a post-test generation partial scan method, called hard fault distribution (HFD), is proposed. The goals of this approach are to have the ability of co-operating with any test pattern generator and to obtain maximum fault coverage for the number of flip-flops selected to be scanned. The concept of the HFD method consists of the essence of previous relative works such as testability analysis, structure analysis and test generation based methods. This method has been applied to several sequential benchmark circuits by co-operating with a simulation-based directed-search test generator. Experimental results show that this HFD method is very efficient.
Original language | English |
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Pages (from-to) | 457-463 |
Number of pages | 7 |
Journal | IEE Proceedings E: Computers and Digital Techniques |
Volume | 139 |
Issue number | 5 |
DOIs | |
Publication status | Published - 1992 Jan 1 |
All Science Journal Classification (ASJC) codes
- General Computer Science
- General Engineering