New representation for programmable logic arrays to facilitate testing and logic design

Jing Jou Tang, Kuen-Jong Lee, Bin-Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). Through this graph model, most realistic PLA faults, including crosspoint, stuck-at, break and bridging faults, can be modeled. The work of diagnosis and test generation is thus simplified. Also many logic design problems such as folding, minimization and decomposition can be done using this representation.

Original languageEnglish
Title of host publicationProceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering
PublisherPubl by IEEE
Pages561-564
Number of pages4
ISBN (Print)0780312333
Publication statusPublished - 1993
EventProceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) - Beijing, China
Duration: 1993 Oct 191993 Oct 21

Other

OtherProceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5)
CityBeijing, China
Period93-10-1993-10-21

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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