Abstract
In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). Through this graph model, most realistic PLA faults, including crosspoint, stuck-at, break and bridging faults, can be modeled. The work of diagnosis and test generation is thus simplified. Also many logic design problems such as folding, minimization and decomposition can be done using this representation.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering |
| Publisher | Publ by IEEE |
| Pages | 561-564 |
| Number of pages | 4 |
| ISBN (Print) | 0780312333 |
| Publication status | Published - 1993 |
| Event | Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) - Beijing, China Duration: 1993 Oct 19 → 1993 Oct 21 |
Other
| Other | Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) |
|---|---|
| City | Beijing, China |
| Period | 93-10-19 → 93-10-21 |
All Science Journal Classification (ASJC) codes
- General Engineering