NEW THREE-LAYER DETAILED ROUTER FOR VLSI LAYOUT.

Jer Min Jou, Jau Yien Lee, Jhing Fa Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A three-layer detailed router that is capable of routing a rectilinear wiring area containing obstacles such as prerouted pins is presented. It supports pins fixed on all sides of the area. A routing methodology is developed; it is basically a divide-and-conquer that partitions the routing area into subones by specially chosen cut lines and then uses a concurrently bidirectional column scanning approach to route each subregion. In each column, a signal column maze router with backtracking is developed. This router consistently outperforms several known routers in quality of wiring.

Original languageEnglish
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages382-385
Number of pages4
ISBN (Print)0818608145
Publication statusPublished - 1987 Dec 1

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Jou, J. M., Lee, J. Y., & Wang, J. F. (1987). NEW THREE-LAYER DETAILED ROUTER FOR VLSI LAYOUT. In Unknown Host Publication Title (pp. 382-385). IEEE.