TY - GEN
T1 - Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)
AU - Kim, Jiyoung
AU - Hong, Augustin J.
AU - Ogawa, Masaaki
AU - Siguang, Ma
AU - Song, Emil B.
AU - Lin, You Sheng
AU - Han, Jeonghee
AU - Chung, U. In
AU - Wang, Kang L.
PY - 2008
Y1 - 2008
N2 - A 3-D Flash memory cell of VRAT (Vertical-Recess-Array-Transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (Planarized Integration on the same PlanE), which allows for the successful implementation of ultra high density Flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.
AB - A 3-D Flash memory cell of VRAT (Vertical-Recess-Array-Transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (Planarized Integration on the same PlanE), which allows for the successful implementation of ultra high density Flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.
UR - http://www.scopus.com/inward/record.url?scp=51949111083&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51949111083&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2008.4588587
DO - 10.1109/VLSIT.2008.4588587
M3 - Conference contribution
AN - SCOPUS:51949111083
SN - 9781424418053
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 122
EP - 123
BT - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
T2 - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Y2 - 17 June 2008 through 19 June 2008
ER -