Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

Jiyoung Kim, Augustin J. Hong, Masaaki Ogawa, Ma Siguang, Emil B. Song, You Sheng Lin, Jeonghee Han, U. In Chung, Kang L. Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

38 Citations (Scopus)

Abstract

A 3-D Flash memory cell of VRAT (Vertical-Recess-Array-Transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (Planarized Integration on the same PlanE), which allows for the successful implementation of ultra high density Flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.

Original languageEnglish
Title of host publication2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Pages122-123
Number of pages2
DOIs
Publication statusPublished - 2008
Event2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States
Duration: 2008 Jun 172008 Jun 19

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
CountryUnited States
CityHonolulu, HI
Period08-06-1708-06-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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