Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

Jiyoung Kim; Augustin J. Hong; Masaaki Ogawa; Ma Siguang; Emil B. Song; You Sheng Lin; Jeonghee Han; U. In Chung; Kang L. Wang

doi:10.1109/VLSIT.2008.4588587

Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

Jiyoung Kim, Augustin J. Hong, Masaaki Ogawa, Ma Siguang, Emil B. Song, You Sheng Lin, Jeonghee Han, U. In Chung, Kang L. Wang

College of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

43 Citations (Scopus)

Abstract

A 3-D Flash memory cell of VRAT (Vertical-Recess-Array-Transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (Planarized Integration on the same PlanE), which allows for the successful implementation of ultra high density Flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.

Original language	English
Title of host publication	2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Pages	122-123
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2008.4588587
Publication status	Published - 2008
Event	2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States Duration: 2008 Jun 17 → 2008 Jun 19

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Country/Territory	United States
City	Honolulu, HI
Period	08-06-17 → 08-06-19

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2008.4588587

Cite this

Kim, J., Hong, A. J., Ogawa, M., Siguang, M., Song, E. B., Lin, Y. S., Han, J., Chung, U. I., & Wang, K. L. (2008). Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE). In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT (pp. 122-123). [4588587] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588587

@inproceedings{92a894bc82994bb59f82f3e404dc6647,

title = "Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)",

abstract = "A 3-D Flash memory cell of VRAT (Vertical-Recess-Array-Transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (Planarized Integration on the same PlanE), which allows for the successful implementation of ultra high density Flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.",

author = "Jiyoung Kim and Hong, {Augustin J.} and Masaaki Ogawa and Ma Siguang and Song, {Emil B.} and Lin, {You Sheng} and Jeonghee Han and Chung, {U. In} and Wang, {Kang L.}",

year = "2008",

doi = "10.1109/VLSIT.2008.4588587",

language = "English",

isbn = "9781424418053",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "122--123",

booktitle = "2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT",

note = "2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT ; Conference date: 17-06-2008 Through 19-06-2008",

}

Kim, J, Hong, AJ, Ogawa, M, Siguang, M, Song, EB, Lin, YS, Han, J, Chung, UI & Wang, KL 2008, Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE). in 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT., 4588587, Digest of Technical Papers - Symposium on VLSI Technology, pp. 122-123, 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT, Honolulu, HI, United States, 08-06-17. https://doi.org/10.1109/VLSIT.2008.4588587

Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE). / Kim, Jiyoung; Hong, Augustin J.; Ogawa, Masaaki et al.

2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. p. 122-123 4588587 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

AU - Kim, Jiyoung

AU - Hong, Augustin J.

AU - Ogawa, Masaaki

AU - Siguang, Ma

AU - Song, Emil B.

AU - Lin, You Sheng

AU - Han, Jeonghee

AU - Chung, U. In

AU - Wang, Kang L.

PY - 2008

Y1 - 2008

N2 - A 3-D Flash memory cell of VRAT (Vertical-Recess-Array-Transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (Planarized Integration on the same PlanE), which allows for the successful implementation of ultra high density Flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.

AB - A 3-D Flash memory cell of VRAT (Vertical-Recess-Array-Transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (Planarized Integration on the same PlanE), which allows for the successful implementation of ultra high density Flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.

UR - http://www.scopus.com/inward/record.url?scp=51949111083&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51949111083&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2008.4588587

DO - 10.1109/VLSIT.2008.4588587

M3 - Conference contribution

AN - SCOPUS:51949111083

SN - 9781424418053

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 122

EP - 123

BT - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT

T2 - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT

Y2 - 17 June 2008 through 19 June 2008

ER -

Kim J, Hong AJ, Ogawa M, Siguang M, Song EB, Lin YS et al. Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE). In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. p. 122-123. 4588587. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588587

Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

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