Novel design of thermal-via configurations for collector-up HBTs

Pei Hsuan Lee, Hsien Cheng Tseng, Jung Hua Chou

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

We devise a finite-element model to analyze the thermal performance of collector-up (C-up) heterojunction bipolar transistors (HBTs) with a thermal-via configuration. A demonstration on the GaInP/GaAs C-up HBT is presented in this Brief, and the novelty of this work is that both 2D and 3D temperature- distribution analyses are performed. The 2D results indicate that the original thermal-via configuration can be reduced by 29%. Furthermore, the results show that the maximum temperature within the collector calculated from 3D analysis is lower than that from the 2D analysis. Based on the 3D analysis, it is revealed that the reported configuration can be reduced by 32%. Therefore, the C-up HBT with a compact thermal-via should be helpful for miniaturization of heat-dissipation packaging configurations within HBT-based high-power amplifiers.

Original languageEnglish
Pages (from-to)445011-445013
Number of pages3
JournalJournal of Electronic Packaging, Transactions of the ASME
Volume131
Issue number4
DOIs
Publication statusPublished - 2009 Dec 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Mechanics of Materials
  • Computer Science Applications
  • Electrical and Electronic Engineering

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