Novel high-density low-power high-performance double-gate logic techniques

Meng Hsueh Chiang, Keunwoo Kim, Christophe Tretz, Ching Te Chuang

Research output: Contribution to journalConference articlepeer-review

16 Citations (Scopus)


Double-gate logic circuit schemes were developed using symmetrical gates for NOR, NAND, and pass gates, in order to reduce the area of the leakage/ active power. The performance improvement and the power reduction for NAND, NOR, and pass gates were studied via the two dimensional numeric device simulator, called MEDICI. It was found that since symmetrical double-gate devices have two identical channels near the front and the back surfaces, the number of transistors required to implement a given logic function could be reduced when the two gates were operated independently. The power/performance advantages were evaluated and demonstrated using the two dimensional numerical device simulator to directly simulate the circuit structures.

Original languageEnglish
Pages (from-to)122-123
Number of pages2
JournalProceedings - IEEE International SOI Conference
Publication statusPublished - 2004 Dec 1
Event2004 IEEE International SOI Conference, Proceedings - Charleston, SC, United States
Duration: 2004 Oct 42004 Oct 7

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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