Novel high-density low-power logic circuit techniques using DG devices

Meng Hsueh Chiang, Keunwoo Kim, Christophe Tretz, Ching Te Chuang

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front- and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.

Original languageEnglish
Pages (from-to)2339-2342
Number of pages4
JournalIEEE Transactions on Electron Devices
Volume52
Issue number10
DOIs
Publication statusPublished - 2005 Oct 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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