Novel high-density low-power logic circuit techniques using DG devices

Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front- and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.