The capture-emission process in a semiconductor sample was greatly affected by a varying electric field in DLTS analysis. The sample was an n-type GaAs layer grown on a 〈100〉-oriented seimi-insulating substrate by molecular beam epitaxy. An Ec - 0.5 eV electron trap level was found under lower bias voltage (-6 V) while both Ec - 0.40 eV and Ec - 0.50 eV traps were observed under higher bias voltage (-7.0 to -8.0 V). Emission rates have been measured that increased with increasing bias voltage from 0 V to -5 V and then decreased when biases were higher than -5 V. In the capacitance transient, when it revealed a delay, two levels, namely at -0.4 and -0.5 eV, appeared in the DLTS signals. However, the EL2 trap (Ec - 0.78 eV), found on another sample, revealed monotonically increasing emission with increasing bias. An explanation of these phenomena was proposed in light of the interaction of these two levels due to the electric field effect.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry