On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains

Kuen-Jong Lee, Bo Ren Chen, Michael Andreas Kochte

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents a novel test architecture that combines the advantages of high-quality deterministic scan-based test and low-cost built-in self-test. The main idea is to record (store) all required compressed test data in a novel scan chain structure, and extract and decompress them during testing. This requires a very high compression ratio to obtain a low test data volume, that is, smaller than the number of scan cells in the circuit under test. To achieve such a high compression ratio, we propose a novel compression method that combines broadcast scan as well as a tailored single-input compression architecture. We also utilize the concept of scan chain partitioning and clock gating to reduce the test time and test power. An on-chip test controller is employed to automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external automatic test equipment. Experimental results show that our method is well suitable for multicore designs. For example, experiments on the 8-core open-source OpenSPARC T2 processor with 5.7M gates show that all required test data for 100% testable stuck-at fault coverage can be stored in just 59.4% of the scan cells of the processor. Experimental results for transition faults are also presented, which show that more identical cores are needed in order to store all test data for transition faults. We also discuss how to extend this paper to address fault diagnosis and engineering change order problems.

Original languageEnglish
Article number8299475
Pages (from-to)309-321
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume38
Issue number2
DOIs
Publication statusPublished - 2019 Feb 1

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Built-in self test
Failure analysis
Clocks
Controllers
Networks (circuits)
Testing
Costs
Experiments

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. / Lee, Kuen-Jong; Chen, Bo Ren; Kochte, Michael Andreas.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 2, 8299475, 01.02.2019, p. 309-321.

Research output: Contribution to journalArticle

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