On-chip SOC test platform design based on IEEE 1500 standard

Kuen Jong Lee, Tong Yu Hsieh, Ching Yao Chang, Yu Ting Hong, Wen Cheng Huang

Research output: Contribution to journalArticlepeer-review

11 Citations (Scopus)


IEEE 1500 Standard defines a standard test interface for embedded cores of a system-on-a-chip (SOC) to simplify the test problems. In this paper we present a systematic method to employ this standard in a SOC test platform so as to carry out on-chip at-speed testing for embedded SOC cores without using expensive external automatic test equipment. The cores that can be handled include scan-based logic cores, BIST-based memory cores, BIST-based mixed-signal devices, and hierarchical cores. All required test control signals for these cores can be generated on-chip by a single centralized test access mechanism (TAM) controller. These control signals along with test data formatted in a single buffer are transferred to the cores via a dedicated test bus, which facilitates parallel core testing. A number of design techniques, including on-chip comparison, direct memory access, hierarchical core test architecture, and hierarchical test bus design, are also employed to enhance the efficiency of the test platform. A sample SOC equipped with the test platform has been designed. Experimental results on both FPGA prototyping and real chip implementation confirm that the test platform can efficiently execute all test procedures and effectively identify potential defect(s) in the target circuit(s).

Original languageEnglish
Article number5229351
Pages (from-to)1134-1139
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
Publication statusPublished - 2010 Jul 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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