On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding

Po Yuan Chen, Cheng Wen Wu, Ding Ming Kwai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

111 Citations (Scopus)

Abstract

Pre-bond test is preferred for a three-dimensional integrated circuit (3D IC), since it reduces stacking yield loss and thus saves cost. In this paper, we present two schemes for testing through-silicon vias (TSVs) by performing on-chip screening before wafer thinning and bonding. The first scheme is for blind TSVs, which have one end floating, using a charge-sharing technique commonly seen in DRAM. The second scheme is for open-sleeve TSVs, which have one end shorted to the substrate, using a voltage-dividing technique commonly seen in ROM. By virtue of the inherent capacitive and resistive characteristics, we detect the TSVs out of a specified range as anomalies, taking into account the effects of process variations in the detection circuitry. The statistical design by Monte Carlo simulation using TSMC 65nm low-power process shows that for blind TSVs, the best overkill ratio is below 6%. For open-sleeve TSVs, inherent limitations restrict the applicability, so more work needs to be done in the future. Our implementation enjoys little area overhead, requiring only a simple sense amplifier and a write buffer that are shared among a number of TSVs. Reducing the number of TSVs that share a test module will reduce the test time, but increase the area overhead. For blind TSVs, the parallelism also affects the overkill and escape rates.

Original languageEnglish
Title of host publicationProceedings - 28th IEEE VLSI Test Symposium, VTS10
Pages263-268
Number of pages6
DOIs
Publication statusPublished - 2010 Jun 29
Event28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States
Duration: 2010 Apr 192010 Apr 22

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference28th IEEE VLSI Test Symposium, VTS10
CountryUnited States
CitySanta Cruz, CA
Period10-04-1910-04-22

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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  • Cite this

    Chen, P. Y., Wu, C. W., & Kwai, D. M. (2010). On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. In Proceedings - 28th IEEE VLSI Test Symposium, VTS10 (pp. 263-268). [5469559] (Proceedings of the IEEE VLSI Test Symposium). https://doi.org/10.1109/VTS.2010.5469559