Abstract
Modern on-chip communication protocols such as advanced eXtensible interface and open core protocol support advanced transactions to improve communication efficiency. Out-of-order transactions that allow responses to be returned in an order different from their request order play an important role in this improvement. However, a deadlock situation may occur if these transactions are not properly manipulated. In this paper, we address the deadlock problem in an on-chip bus system supporting out-of-order transactions. We present a graphic model that can well represent the status of a bus system and show that a cycle exists in the graph if and only if the bus system is in an unsafe state that may lead to a bus deadlock. Based on this model, we propose a novel bus design technique that can efficiently resolve the bus deadlock problem. Experimental results show that buses with the proposed technique can be up to 3.3 times faster than those with the currently available techniques.
| Original language | English |
|---|---|
| Article number | 6490417 |
| Pages (from-to) | 484-496 |
| Number of pages | 13 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 22 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2014 Jan 1 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
}
On deadlock problem of on-chip buses supporting out-of-order transactions. / Chang, Chin Yao; Lee, Kuen-Jong.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 3, 6490417, 01.01.2014, p. 484-496.Research output: Contribution to journal › Article
TY - JOUR
T1 - On deadlock problem of on-chip buses supporting out-of-order transactions
AU - Chang, Chin Yao
AU - Lee, Kuen-Jong
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Modern on-chip communication protocols such as advanced eXtensible interface and open core protocol support advanced transactions to improve communication efficiency. Out-of-order transactions that allow responses to be returned in an order different from their request order play an important role in this improvement. However, a deadlock situation may occur if these transactions are not properly manipulated. In this paper, we address the deadlock problem in an on-chip bus system supporting out-of-order transactions. We present a graphic model that can well represent the status of a bus system and show that a cycle exists in the graph if and only if the bus system is in an unsafe state that may lead to a bus deadlock. Based on this model, we propose a novel bus design technique that can efficiently resolve the bus deadlock problem. Experimental results show that buses with the proposed technique can be up to 3.3 times faster than those with the currently available techniques.
AB - Modern on-chip communication protocols such as advanced eXtensible interface and open core protocol support advanced transactions to improve communication efficiency. Out-of-order transactions that allow responses to be returned in an order different from their request order play an important role in this improvement. However, a deadlock situation may occur if these transactions are not properly manipulated. In this paper, we address the deadlock problem in an on-chip bus system supporting out-of-order transactions. We present a graphic model that can well represent the status of a bus system and show that a cycle exists in the graph if and only if the bus system is in an unsafe state that may lead to a bus deadlock. Based on this model, we propose a novel bus design technique that can efficiently resolve the bus deadlock problem. Experimental results show that buses with the proposed technique can be up to 3.3 times faster than those with the currently available techniques.
UR - http://www.scopus.com/inward/record.url?scp=84895923129&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84895923129&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2013.2248765
DO - 10.1109/TVLSI.2013.2248765
M3 - Article
AN - SCOPUS:84895923129
VL - 22
SP - 484
EP - 496
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 3
M1 - 6490417
ER -