On feasibility of HOY - A wireless test methodology for VLSI chips and wafers

Po Kai Chen, Yu Tsao Hsing, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages243-246
Number of pages4
DOIs
Publication statusPublished - 2007 Oct 1
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan
Duration: 2007 Apr 262007 Apr 28

Publication series

Name2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Other

Other2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CountryTaiwan
CityHsinchu
Period07-04-2607-04-28

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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