A practical 3-D integration approach is to stack a number of dies on a passive silicon interposer base, which consists of only TSVs and metal wires to implement interconnects. In normal mode, the tristate buffers are controlled according to the repair signatures. The NVM can be any storage devices which have at least onetime programmability and can retain data when power is off, such as Flash memory, one time-programmable read-only memory (ROM), and so on. The JTAG interface is reused to control the BIST module. Main components of the proposed BIST include a BIST controller to coordinate test operations, a pattern generator to generate predesigned test patterns, and a response comparator to compare between expected and actual responses. The test patterns embedded in the BIST are up-transition and down transition patterns, which can detect slow-to-rise and slow-to-fall behaviors on interconnects. The transition launched will be captured at the other end of the interconnects after one clock cycle, achieving at-speed launch and capture.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering