On the design of a fault-tolerant systolic array multiplier using time redundancy

T.-Y. Chang, C.-C. Wang, J.-B. Shu, Cheng-Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationInternational Symposium on IC Design and Manufacturing (ISIC)
Place of PublicationSingapore
Pages497-502
Publication statusPublished - 1991 Sep

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