On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation

Kuen Jong Lee, Jing Jou Tang, Wern Yih Duh

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

An accurate threshold voltage determination method for CMOS gates is presented that can be used to enhance the performance of test generation (TPG) and fault simulation (FS). By using this model the `Byzantine General' problem during the FS and TPG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation.

Original languageEnglish
Pages (from-to)113-118
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 1998 Dec 1
EventProceedings of the 1998 7th Asian Test Symposium - Singapore, Singapore
Duration: 1998 Dec 21998 Dec 4

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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