On the high-performance Ti-salicide ULSI CMOS devices prepared by a borderless contact technique and double-implant structure

Kong Beng Thei, Hung Ming Chuang, Kuo Hui Yu, Wen-Chau Liu, Rong Chau Liu, Kun Wei Lin, Chi Wen Su, Chin Shiung Ho, Shou Gwo Wuu, Chung Shu Wang

Research output: Contribution to journalArticlepeer-review

Abstract

A borderless contact (BLC) technique and double-implant structure (DIS) have been developed successfully to fabricate high-performance Ti-salicide sub-quarter-micron CMOS devices. A SiOxNy film grown by low-temperature chemical vapour deposition is used to act as the selective etch-stop layer. The n+ and p+ DIS can reduce the junction leakage current which is usually enhanced by BLC etching near the edge of shallow trench isolation. Based on the use of the BLC process, the process window can be enlarged. In addition, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration. Experimentally, by combining the BLC and DIS techniques, low leakage and low sheet resistance CMOS devices and low standby current and high yield 1 Mb SRAMs are fabricated successfully.

Original languageEnglish
Pages (from-to)205-210
Number of pages6
JournalSemiconductor Science and Technology
Volume17
Issue number3
DOIs
Publication statusPublished - 2002 Mar 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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