On the implementation of wave-pipelined multipliers in lookup table-based FPGAs

Yuan Shuenn Ke, Ming-Der Shieh, Ming Hwa Sheu

Research output: Contribution to conferencePaperpeer-review

Abstract

In this paper, the performance evaluation and implementation of wave-pipelined multipliers in lookup table-based FPGAs are presented. Based on our proposed methodology, high-speed wave-pipelined multipliers have been successfully implemented in the Xilinx XC4000 series. The developed structure can be applied for the multiplication of two unsigned numbers or two two's complement numbers. Compared with the previous work, our measured results are better in terms of maximum difference of path delays, operating frequency, and the number of LUTs used. The results are promising and the design is well suitable for high-performance systems implemented in FPGAs.

Original languageEnglish
Pages434-437
Number of pages4
Publication statusPublished - 1997 Dec 1
Event7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore
Duration: 1997 Sep 101997 Sep 12

Other

Other7th International Symposium on IC Technology, Systems and Applications ISIC 97
Country/TerritorySingapore
CitySingapore
Period97-09-1097-09-12

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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