On the implementation of wave-pipelined multipliers in lookup table-based FPGAs

Yuan Shuenn Ke; Ming Der Shieh; Ming Hwa Sheu

On the implementation of wave-pipelined multipliers in lookup table-based FPGAs

Yuan Shuenn Ke
, Ming Der Shieh
, Ming Hwa Sheu

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, the performance evaluation and implementation of wave-pipelined multipliers in lookup table-based FPGAs are presented. Based on our proposed methodology, high-speed wave-pipelined multipliers have been successfully implemented in the Xilinx XC4000 series. The developed structure can be applied for the multiplication of two unsigned numbers or two two's complement numbers. Compared with the previous work, our measured results are better in terms of maximum difference of path delays, operating frequency, and the number of LUTs used. The results are promising and the design is well suitable for high-performance systems implemented in FPGAs.

Original language	English
Pages	434-437
Number of pages	4
Publication status	Published - 1997
Event	7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore Duration: 1997 Sept 10 → 1997 Sept 12

Other

Other	7th International Symposium on IC Technology, Systems and Applications ISIC 97
Country/Territory	Singapore
City	Singapore
Period	97-09-10 → 97-09-12

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "On the implementation of wave-pipelined multipliers in lookup table-based FPGAs",

abstract = "In this paper, the performance evaluation and implementation of wave-pipelined multipliers in lookup table-based FPGAs are presented. Based on our proposed methodology, high-speed wave-pipelined multipliers have been successfully implemented in the Xilinx XC4000 series. The developed structure can be applied for the multiplication of two unsigned numbers or two two's complement numbers. Compared with the previous work, our measured results are better in terms of maximum difference of path delays, operating frequency, and the number of LUTs used. The results are promising and the design is well suitable for high-performance systems implemented in FPGAs.",

author = "Ke, \{Yuan Shuenn\} and Shieh, \{Ming Der\} and Sheu, \{Ming Hwa\}",

year = "1997",

language = "English",

pages = "434--437",

note = "7th International Symposium on IC Technology, Systems and Applications ISIC 97 ; Conference date: 10-09-1997 Through 12-09-1997",

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T1 - On the implementation of wave-pipelined multipliers in lookup table-based FPGAs

AU - Ke, Yuan Shuenn

AU - Shieh, Ming Der

AU - Sheu, Ming Hwa

PY - 1997

Y1 - 1997

N2 - In this paper, the performance evaluation and implementation of wave-pipelined multipliers in lookup table-based FPGAs are presented. Based on our proposed methodology, high-speed wave-pipelined multipliers have been successfully implemented in the Xilinx XC4000 series. The developed structure can be applied for the multiplication of two unsigned numbers or two two's complement numbers. Compared with the previous work, our measured results are better in terms of maximum difference of path delays, operating frequency, and the number of LUTs used. The results are promising and the design is well suitable for high-performance systems implemented in FPGAs.

AB - In this paper, the performance evaluation and implementation of wave-pipelined multipliers in lookup table-based FPGAs are presented. Based on our proposed methodology, high-speed wave-pipelined multipliers have been successfully implemented in the Xilinx XC4000 series. The developed structure can be applied for the multiplication of two unsigned numbers or two two's complement numbers. Compared with the previous work, our measured results are better in terms of maximum difference of path delays, operating frequency, and the number of LUTs used. The results are promising and the design is well suitable for high-performance systems implemented in FPGAs.

UR - https://www.scopus.com/pages/publications/1842679164

UR - https://www.scopus.com/pages/publications/1842679164#tab=citedBy

M3 - Paper

AN - SCOPUS:1842679164

SP - 434

EP - 437

T2 - 7th International Symposium on IC Technology, Systems and Applications ISIC 97

Y2 - 10 September 1997 through 12 September 1997

ER -

On the implementation of wave-pipelined multipliers in lookup table-based FPGAs

Abstract

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All Science Journal Classification (ASJC) codes

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