TY - JOUR
T1 - On the temperature-dependent characteristics of a Pd/InAlAs based electroless-plating gate metamorphic heterostructure field-effect transistor (MHFET)
AU - Huang, Chien Chang
AU - Chen, Huey Ing
AU - Chen, Tai You
AU - Hsu, Chi Shiang
AU - Chen, Chun Chia
AU - Chang, Hsuan Sheng
AU - Liu, Wen Chau
N1 - Funding Information:
Part of this work was supported by the National Science Council of the Republic of China under Contract No. NSC-97-2221-E-006-238-MY3. The authors are also grateful to National Nano Device Laboratories (NDL) for RF measurements.
PY - 2013/1
Y1 - 2013/1
N2 - In this work, the interesting temperature-dependent characteristics of a Pd/InAlAs based metamorphic heterostructure field-effect transistor (MHFET) with an electroless plating (EP)-gate approach are demonstrated and studied. Based on the low-energy and low-temperature chemical deposition, the EP technique can reduce the thermal damage and disordered-states to form a better metal-semiconductor (MS) interface. The EP-gate device shows better performance including higher turn-on voltage (0.978 V), lower gate leakage current (2.1 μA/mm), higher Schottky barrier height (0.742 eV), lower ideality factor (1.15), higher transconductance (272.4 mS/mm), higher drain saturation current (420.2 mA/mm), wider IDS operating region (291.3 mA/mm), and higher voltage gain (449.7) than a thermal evaporation (TE)-gate one over a wide temperature range (300-420 K).
AB - In this work, the interesting temperature-dependent characteristics of a Pd/InAlAs based metamorphic heterostructure field-effect transistor (MHFET) with an electroless plating (EP)-gate approach are demonstrated and studied. Based on the low-energy and low-temperature chemical deposition, the EP technique can reduce the thermal damage and disordered-states to form a better metal-semiconductor (MS) interface. The EP-gate device shows better performance including higher turn-on voltage (0.978 V), lower gate leakage current (2.1 μA/mm), higher Schottky barrier height (0.742 eV), lower ideality factor (1.15), higher transconductance (272.4 mS/mm), higher drain saturation current (420.2 mA/mm), wider IDS operating region (291.3 mA/mm), and higher voltage gain (449.7) than a thermal evaporation (TE)-gate one over a wide temperature range (300-420 K).
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U2 - 10.1016/j.sse.2012.05.063
DO - 10.1016/j.sse.2012.05.063
M3 - Article
AN - SCOPUS:84869496152
SN - 0038-1101
VL - 79
SP - 50
EP - 55
JO - Solid-State Electronics
JF - Solid-State Electronics
ER -