One-dimensional approach for floating field limiting ring enhanced high-voltage power transistor design

B. D. Liu, C. T. Sune

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

A new analytic method that combines models of a plane junction in bulk and a cylindrical junction at a surface, is proposed. From this analysis, the optimal space between the base junction and the floating field limiting ring of a power transistor are obtained. The influences of the concentration and thickness of a lightly doped collector layer, the base junction depth and the applied voltage on the optimal space are also discussed. The deviation between the results obtained from this model and two-dimensional numerical solutions is within 5%. Experimental results obtained using high-voltage power transistors based on this approach are in agreement with theoretical predictions.

Original languageEnglish
Pages (from-to)891-899
Number of pages9
JournalInternational Journal of Electronics
Volume66
Issue number6
DOIs
Publication statusPublished - 1989 Jun

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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