Optimal design and performance assessment of extremely-scaled Si nanowire FET on insulator

Chun Yu Chen, Yi Bo Liao, Meng Hsueh Chiang, Keunwoo Kim, Wei Chou Hsu, Shiou Ying Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the wire diameter could achieve performance benefits in the nanowire FET technologies. Small wire diameter is not necessary for performance, though it favors device scaling.

Original languageEnglish
Title of host publication2009 IEEE International SOI Conference
DOIs
Publication statusPublished - 2009
Event2009 IEEE International SOI Conference - Foster City, CA, United States
Duration: 2009 Oct 52009 Oct 8

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X

Other

Other2009 IEEE International SOI Conference
CountryUnited States
CityFoster City, CA
Period09-10-0509-10-08

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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