Optimal design of nanoscale triple-gate devices

Meng Hsueh Chiang, Tze Neng Lin, Keunwoo Kim, Ching Te Chuang, Christophe Tretz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publication2006 IEEE international SOI Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages143-144
Number of pages2
ISBN (Print)1424402905, 9781424402908
DOIs
Publication statusPublished - 2006 Jan 1
Event2006 IEEE International Silicon on Insulator Conference, SOI - Niagara Falls, NY, United States
Duration: 2006 Oct 22006 Oct 5

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X

Other

Other2006 IEEE International Silicon on Insulator Conference, SOI
CountryUnited States
CityNiagara Falls, NY
Period06-10-0206-10-05

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Chiang, M. H., Lin, T. N., Kim, K., Chuang, C. T., & Tretz, C. (2006). Optimal design of nanoscale triple-gate devices. In 2006 IEEE international SOI Conference Proceedings (pp. 143-144). [4062924] (Proceedings - IEEE International SOI Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOI.2006.284476