Optimization of gate-on-source-only tunnel FETs with counter-doped pockets

Kuo Hsing Kao, Anne S. Verhulst, William G. Vandenberghe, Bart Sorée, Wim Magnus, Daniele Leonelli, Guido Groeseneken, Kristin De Meyer

Research output: Contribution to journalArticle

77 Citations (Scopus)

Abstract

We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher on-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-source-only tunnel field-effect transistor simulations.

Original languageEnglish
Article number6226449
Pages (from-to)2070-2077
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume59
Issue number8
DOIs
Publication statusPublished - 2012 Jul 3

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Kao, K. H., Verhulst, A. S., Vandenberghe, W. G., Sorée, B., Magnus, W., Leonelli, D., Groeseneken, G., & De Meyer, K. (2012). Optimization of gate-on-source-only tunnel FETs with counter-doped pockets. IEEE Transactions on Electron Devices, 59(8), 2070-2077. [6226449]. https://doi.org/10.1109/TED.2012.2200489