Origin of stress memorization mechanism in strained-Si nMOSFETs using a low-cost stress-memorization technique

Yao Tsung Huang; San Lein Wu; Shoou Jinn Chang; Cheng Wen Kuo; Ya Ting Chen; Yao Chin Cheng; Osbert Cheng

doi:10.1109/TNANO.2010.2103567

Origin of stress memorization mechanism in strained-Si nMOSFETs using a low-cost stress-memorization technique

Yao Tsung Huang, San Lein Wu, Shoou Jinn Chang, Cheng Wen Kuo, Ya Ting Chen, Yao Chin Cheng, Osbert Cheng

Institute of Microelectronics

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with 100channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain L_S/D and polyspacing) on the device performance. In the SMT devices with L_S/D down to 0.11 m and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.

Original language	English
Article number	5678837
Pages (from-to)	1053-1058
Number of pages	6
Journal	IEEE Transactions on Nanotechnology
Volume	10
Issue number	5
DOIs	https://doi.org/10.1109/TNANO.2010.2103567
Publication status	Published - 2011 Sept

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

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title = "Origin of stress memorization mechanism in strained-Si nMOSFETs using a low-cost stress-memorization technique",

abstract = "Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with 100channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D and polyspacing) on the device performance. In the SMT devices with LS/D down to 0.11 m and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.",

author = "Huang, {Yao Tsung} and Wu, {San Lein} and Chang, {Shoou Jinn} and Kuo, {Cheng Wen} and Chen, {Ya Ting} and Cheng, {Yao Chin} and Osbert Cheng",

note = "Funding Information: Manuscript received March 10 2009; revised November 10, 2009, March 18, 2010, and October 2, 2010; accepted December 19, 2010. Date of publication January 6, 2011; date of current version September 8, 2011. This work was supported in part by the National Science Council (NSC) of Taiwan under Contract NSC 99-2221-E-230-019, in part by the Center for Frontier Materials and Micro/Nano Science and Technology, National Cheng Kung University, Taiwan, under Contract D97-2700, and in part by the Advanced Optoelectronic Technology Center, National Cheng Kung University, under projects from the Ministry of Education. The review of this paper was arranged by Associate Editor A. A. Balandin.",

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T1 - Origin of stress memorization mechanism in strained-Si nMOSFETs using a low-cost stress-memorization technique

AU - Huang, Yao Tsung

AU - Wu, San Lein

AU - Chang, Shoou Jinn

AU - Kuo, Cheng Wen

AU - Chen, Ya Ting

AU - Cheng, Yao Chin

AU - Cheng, Osbert

N1 - Funding Information: Manuscript received March 10 2009; revised November 10, 2009, March 18, 2010, and October 2, 2010; accepted December 19, 2010. Date of publication January 6, 2011; date of current version September 8, 2011. This work was supported in part by the National Science Council (NSC) of Taiwan under Contract NSC 99-2221-E-230-019, in part by the Center for Frontier Materials and Micro/Nano Science and Technology, National Cheng Kung University, Taiwan, under Contract D97-2700, and in part by the Advanced Optoelectronic Technology Center, National Cheng Kung University, under projects from the Ministry of Education. The review of this paper was arranged by Associate Editor A. A. Balandin.

PY - 2011/9

Y1 - 2011/9

N2 - Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with 100channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D and polyspacing) on the device performance. In the SMT devices with LS/D down to 0.11 m and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.

AB - Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with 100channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D and polyspacing) on the device performance. In the SMT devices with LS/D down to 0.11 m and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.

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Origin of stress memorization mechanism in strained-Si nMOSFETs using a low-cost stress-memorization technique

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