Origin of stress memorization mechanism in strained-Si nMOSFETs using a low-cost stress-memorization technique

Yao Tsung Huang, San Lein Wu, Shoou Jinn Chang, Cheng Wen Kuo, Ya Ting Chen, Yao Chin Cheng, Osbert Cheng

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with 100channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D and polyspacing) on the device performance. In the SMT devices with LS/D down to 0.11 m and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.

Original languageEnglish
Article number5678837
Pages (from-to)1053-1058
Number of pages6
JournalIEEE Transactions on Nanotechnology
Volume10
Issue number5
DOIs
Publication statusPublished - 2011 Sep

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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