Recently a novel test response compaction method called output bit selection, or simply output selection, is proposed. By observing only a subset of output responses, this method can effectively deal with the aliasing, unknown-value, and low-diagnosis problems. One important issue for output selection is how to implement the selection hardware to obtain a high test response reduction ratio. In this paper a counter-based approach is proposed to implement the output selection method for scan-based designs. Only a counter and a multiplexer are required in this approach, which induce very small area overhead and simple test control. An ATPG-independent output selection algorithm is presented to determine the desired output responses using a set of pre-defined counter operations. Experimental results on large ISCAS'89 and ITC'99 benchmark circuits show that 77%∼89% reduction ratios on test responses can be achieved with 0.39%∼0.88% area overhead.