Abstract
Recently a novel test response compaction method called output bit selection, or simply output selection, is proposed. By observing only a subset of output responses, this method can effectively deal with the aliasing, unknown-value, and low-diagnosis problems. One important issue for output selection is how to implement the selection hardware to obtain a high test response reduction ratio. In this paper a counter-based approach is proposed to implement the output selection method for scan-based designs. Only a counter and a multiplexer are required in this approach, which induce very small area overhead and simple test control. An ATPG-independent output selection algorithm is presented to determine the desired output responses using a set of pre-defined counter operations. Experimental results on large ISCAS'89 and ITC'99 benchmark circuits show that 77%∼89% reduction ratios on test responses can be achieved with 0.39%∼0.88% area overhead.
| Original language | English |
|---|---|
| Title of host publication | ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings |
| DOIs | |
| Publication status | Published - 2012 Dec 1 |
| Event | 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China Duration: 2012 Oct 29 → 2012 Nov 1 |
Publication series
| Name | ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings |
|---|
Other
| Other | 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 |
|---|---|
| Country | China |
| City | Xi'an |
| Period | 12-10-29 → 12-11-01 |
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All Science Journal Classification (ASJC) codes
- Human-Computer Interaction
- Electrical and Electronic Engineering
Cite this
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Output bit selection for test response compaction based on a single counter. / Lee, Kuen-Jong; Lien, Wei Cheng; Hsieh, Tong Yu.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467671 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Output bit selection for test response compaction based on a single counter
AU - Lee, Kuen-Jong
AU - Lien, Wei Cheng
AU - Hsieh, Tong Yu
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Recently a novel test response compaction method called output bit selection, or simply output selection, is proposed. By observing only a subset of output responses, this method can effectively deal with the aliasing, unknown-value, and low-diagnosis problems. One important issue for output selection is how to implement the selection hardware to obtain a high test response reduction ratio. In this paper a counter-based approach is proposed to implement the output selection method for scan-based designs. Only a counter and a multiplexer are required in this approach, which induce very small area overhead and simple test control. An ATPG-independent output selection algorithm is presented to determine the desired output responses using a set of pre-defined counter operations. Experimental results on large ISCAS'89 and ITC'99 benchmark circuits show that 77%∼89% reduction ratios on test responses can be achieved with 0.39%∼0.88% area overhead.
AB - Recently a novel test response compaction method called output bit selection, or simply output selection, is proposed. By observing only a subset of output responses, this method can effectively deal with the aliasing, unknown-value, and low-diagnosis problems. One important issue for output selection is how to implement the selection hardware to obtain a high test response reduction ratio. In this paper a counter-based approach is proposed to implement the output selection method for scan-based designs. Only a counter and a multiplexer are required in this approach, which induce very small area overhead and simple test control. An ATPG-independent output selection algorithm is presented to determine the desired output responses using a set of pre-defined counter operations. Experimental results on large ISCAS'89 and ITC'99 benchmark circuits show that 77%∼89% reduction ratios on test responses can be achieved with 0.39%∼0.88% area overhead.
UR - http://www.scopus.com/inward/record.url?scp=84874856016&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874856016&partnerID=8YFLogxK
U2 - 10.1109/ICSICT.2012.6467671
DO - 10.1109/ICSICT.2012.6467671
M3 - Conference contribution
AN - SCOPUS:84874856016
SN - 9781467324724
T3 - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
BT - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
ER -