Output bit selection for test response compaction based on a single counter

Kuen-Jong Lee, Wei Cheng Lien, Tong Yu Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Recently a novel test response compaction method called output bit selection, or simply output selection, is proposed. By observing only a subset of output responses, this method can effectively deal with the aliasing, unknown-value, and low-diagnosis problems. One important issue for output selection is how to implement the selection hardware to obtain a high test response reduction ratio. In this paper a counter-based approach is proposed to implement the output selection method for scan-based designs. Only a counter and a multiplexer are required in this approach, which induce very small area overhead and simple test control. An ATPG-independent output selection algorithm is presented to determine the desired output responses using a set of pre-defined counter operations. Experimental results on large ISCAS'89 and ITC'99 benchmark circuits show that 77%∼89% reduction ratios on test responses can be achieved with 0.39%∼0.88% area overhead.

Original languageEnglish
Title of host publicationICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China
Duration: 2012 Oct 292012 Nov 1

Publication series

NameICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
CountryChina
CityXi'an
Period12-10-2912-11-01

All Science Journal Classification (ASJC) codes

  • Human-Computer Interaction
  • Electrical and Electronic Engineering

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